Verilog code for 4 bit Binary Ripple Counter

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//Ripple counter
module ripplecounter (A0,A1,A2,A3,Count,Reset);
output A0,A1,A2,A3;
input Count,Reset;
//Instantiate complementing flip-flop
CF F0 (A0,Count,Reset);
CF F1 (A1,A0,Reset);
CF F2 (A2,A1,Reset);
CF F3 (A3,A2,Reset);
endmodule

//Complementing flip-flop with delay
//Input to D flip-flop = Q'
module CF (Q,CLK,Reset);
output Q;
input CLK,Reset;
reg Q;
always @ (negedge CLK or posedge Reset)
if (Reset) Q = 1'b0;
else Q = #2 (~Q); // Delay of 2 time units
endmodule


//Stimulus for testing ripple counter

module testcounter;
reg Count;
reg Reset;
wire A0,A1,A2,A3;
//Instantiate ripple counter
ripplecounter RC (A0,A1,A2,A3,Count,Reset);
always
#5 Count = ~Count;
initial
begin
Count = 1'b0;
Reset = 1'b1;
#4 Reset = 1'b0;
#165 $finish;
end
endmodule